1. Technical Field
Embodiments of the present disclosure may generally relate to a latency control device and a semiconductor device including the same, and more particularly to a technology for testing a latency operation of the semiconductor device.
2. Related Art
With increasing integration of semiconductor memory devices, operation speeds of the semiconductor memory devices have also been continuously improved. In order to increase operation speeds of semiconductor memory devices, synchronous memory devices capable of operating by synchronizing with an external clock of a memory chip have recently been proposed.
A representative example of a synchronous memory device is a single data rate (SDR) synchronous memory device that is synchronized with a rising edge of an external clock of a memory device such that one data piece can be input and/or output at one data pin during one period of the clock.
However, the SDR synchronous memory device has difficulty in satisfying high-speed system operations. In order to solve this, a double data rate (DDR) synchronous memory device capable of processing two pieces of data during one clock period has been proposed.
Two contiguous pieces of data are input and output through respective data input/output (I/O) pins of the DDR synchronous memory device, such that the two contiguous pieces of data are synchronized with a rising edge and a falling edge of an external input clock. Therefore, although a clock frequency of the DDR synchronous memory device is not increased, the DDR synchronous memory device may have a bandwidth that is at least two times larger than that of the SDR synchronous memory device, such that the DDR synchronous memory device can operate at a higher speed than the SDR synchronous memory device.
The DDR synchronous memory device should transmit or receive two pieces of data within one clock period. However, it is impossible for the DDR synchronous memory device to effectively perform the above transmission/reception operation using a conventional data access scheme for use in a conventional synchronous memory device. Therefore, a new data access scheme is needed, which can receive data from the memory device and transmit the received data to an internal region, and can also transmit data received from a core region to an external part.